Semiconductor memory device and method for manufacturing same

ABSTRACT

According to one embodiment, a semiconductor memory device includes a substrate, a semiconductor pillar provided on the substrate to extend in a vertical direction, a plurality of first electrode films provided sideward of the semiconductor pillar to extend in a first direction. The plurality of first electrode films are disposed to be separated from each other along the vertical direction. The semiconductor memory device further includes a plurality of second electrode films provided between the semiconductor pillar and the first electrode films. The plurality of second electrode films are disposed to be separated from each other along the vertical direction. The semiconductor memory device further includes a first insulating film provided between the semiconductor pillar and the second electrode films, and a second insulating film provided between the second electrode film and the first electrode film.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2014-003793, filed on Jan. 10, 2014; theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor memorydevice and a method for manufacturing the same.

BACKGROUND

Although conventionally the planar structure of NAND flash memory hasbeen shrunk to increase the bit density and reduce the bit cost, suchshrink is approaching a limit. Therefore, in recent years, technologyhas been proposed to stack the memory cells in the vertical direction.The data retention characteristics of the memory cells are problematicin such a stacked memory device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view showing a semiconductor memory deviceaccording to a first embodiment;

FIG. 2 is a cross-sectional view showing the semiconductor memory deviceaccording to the first embodiment;

FIG. 3 is a cross-sectional view showing region A shown in FIG. 2;

FIG. 4 is a cross-sectional view along line B-B′ shown in FIG. 2;

FIG. 5A to FIG. 17B are plan views and cross-sectional views showing amethod for manufacturing the semiconductor memory device according tothe first embodiment;

FIG. 18 is a cross-sectional view showing a semiconductor memory deviceaccording to a modification of the first embodiment;

FIG. 19 is a cross-sectional view showing a semiconductor memory deviceaccording to a second embodiment;

FIG. 20A to FIG. 30C are plan views and cross-sectional views showing amethod for manufacturing the semiconductor memory device according tothe second embodiment;

FIG. 31 is a cross-sectional view showing a semiconductor memory deviceaccording to a first modification of the second embodiment;

FIG. 32 is a cross-sectional view showing a semiconductor memory deviceaccording to a second modification of the second embodiment;

FIG. 33 is a cross-sectional view showing a semiconductor memory deviceaccording to a third modification of the second embodiment;

FIG. 34 is a cross-sectional view showing a semiconductor memory deviceaccording to a third embodiment;

FIGS. 35A to 37C are plan views and cross-sectional views showing themethod for manufacturing the semiconductor memory device according tothe third embodiment;

FIGS. 38A to 38C are cross-sectional views showing a semiconductormemory device according to a modification of the third embodiment;

FIGS. 39A to 39C are cross-sectional views showing a method formanufacturing the semiconductor memory device according to themodification of the third embodiment;

FIG. 40 is a cross-sectional view showing a semiconductor memory deviceaccording to a forth embodiment;

FIG. 41 is a cross-sectional view showing region E shown in FIG. 40;

FIG. 42A is a cross-sectional view showing a method for manufacturingthe semiconductor memory device according to the forth embodiment; andFIG. 42B is a plan view;

FIG. 43 and FIG. 44 are cross-sectional views showing a semiconductormemory device according to a fifth embodiment;

FIG. 45 to FIG. 53 are cross-sectional views showing a method formanufacturing the semiconductor memory device according to the fifthembodiment;

FIG. 54 is a cross-sectional view showing a semiconductor memory deviceaccording to a modification of the fifth embodiment; and

FIG. 55 to FIG. 57 are cross-sectional views showing the method formanufacturing the semiconductor memory device according to themodification of the fifth embodiment.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor memory deviceincludes a substrate, a semiconductor pillar provided on the substrateto extend in a vertical direction, a plurality of first electrode filmsprovided sideward of the semiconductor pillar to extend in a firstdirection. The plurality of first electrode films are disposed to beseparated from each other along the vertical direction. Thesemiconductor memory device further includes a plurality of secondelectrode films provided between the semiconductor pillar and the firstelectrode films. The plurality of second electrode films are disposed tobe separated from each other along the vertical direction. Thesemiconductor memory device further includes a first insulating filmprovided between the semiconductor pillar and the second electrodefilms, and a second insulating film provided between the secondelectrode film and the first electrode film.

First Embodiment

Embodiments of the invention will now be described with reference to thedrawings.

First, a first embodiment will be described.

FIG. 1 is a perspective view showing a semiconductor memory deviceaccording to the embodiment.

FIG. 2 is a cross-sectional view showing the semiconductor memory deviceaccording to the embodiment.

FIG. 3 is a cross-sectional view showing region A shown in FIG. 2.

FIG. 4 is a cross-sectional view along line B-B′ shown in FIG. 2.

As shown in FIG. 1 and FIG. 2, a silicon substrate 10 is provided in thesemiconductor memory device 1 according to the embodiment. A memory cellregion Rm and a peripheral circuit region Rc are set in the siliconsubstrate 10. Hereinbelow, an XYZ orthogonal coordinate system isemployed in the specification for convenience of description. Twomutually-orthogonal directions parallel to an upper surface 10 a of thesilicon substrate 10 are taken as an X-direction and a Y-direction; anda direction perpendicular to the upper surface 10 a is taken as aZ-direction.

In the memory cell region Rm, an insulating film 11 (a third insulatingfilm) that is made of, for example, silicon oxide, a conductive layer 12that is made of, for example, polysilicon, an interconnect layer 13 thatis made of, for example, tungsten, and a conductive layer 14 that ismade of, for example, polysilicon are stacked in this order on thesilicon substrate 10. A cell source line 15 is formed of the conductivelayer 12, the interconnect layer 13, and the conductive layer 14. Aninsulating film 17 that is made of, for example, silicon oxide isprovided on the cell source line 15. Multiple silicon pillars 20 thatextend in the Z-direction are provided on the cell source line 15. Thesilicon pillars 20 are made of, for example, polysilicon; and the lowerends of the silicon pillars 20 pierce the insulating film 17 to beconnected to the cell source line 15. The silicon pillars 20 arearranged in a matrix configuration along the X-direction and theY-direction as viewed from the Z-direction and have a common connectionwith a single cell source line 15.

Multiple control gate electrode films (the first electrode films) 21 areprovided sideward of the silicon pillar 20 to be separated from eachother along the Z-direction. Each of the control gate electrode films 21is made of, for example, tungsten and extends in the Y-direction.Therefore, the control gate electrode films 21 are not disposed betweenthe silicon pillars 20 arranged along the Y-direction. Also, in theX-direction, two of the silicon pillars 20 are arranged alternately withtwo of the control gate electrode films 21. In other words, when thesilicon pillars 20 arranged along the X-direction are organized intomultiple sets 22 every two mutually-adjacent silicon pillars 20 and whentwo of the control gate electrode films 21 are arranged to be positionedbetween the sets 22, the control gate electrode films 21 are notdisposed between the two silicon pillars 20 belonging to each set 22.

An inter-layer insulating film 23 is provided between the siliconpillars 20. An inter-layer insulating film 24 that is made of, forexample, silicon oxide is provided between the control gate electrodefilms 21, below the control gate electrode film 21 of the lowermostlayer, and above the control gate electrode film 21 of the uppermostlayer. A hard mask 26 is provided on a stacked body 25 that is made ofthe multiple control gate electrode films 21, the inter-layer insulatingfilm 23, and the inter-layer insulating film 24.

The silicon pillar 20 is drawn out onto the hard mask 26 to be a singlebody with an interconnect 27 extending in the X-direction. Thereby, thesilicon pillars 20 that are arranged along the X-direction are connectedto a common interconnect 27. A via 28 is provided on the interconnect27; and a bit line 29 that extends in the X-direction is provided on thevia 28. The bit line 29 is connected to the interconnect 27 by the via28. Thus, each of the silicon pillars 20 is connected between the bitline 29 and the cell source line 15. In other words, the semiconductormemory device 1 is an I-shaped pillar type stacked memory device.

The Y-direction end portion of the stacked body 25 is patterned into astairstep configuration; and at the end portion of the stairstepconfiguration, the multiple control gate electrode films 21 that havethe same position in the Z-direction are bundled together. A via 38 isprovided on the end portion of the bundled control gate electrode films21. A word line 39 that extends in the Y-direction is provided on thevia 38. In the Z-direction, the position of the word line 39 is the sameas the position of the bit line 29. The word line 39 is connected to thecontrol gate electrode film 21 by the via 38.

As shown in FIG. 3 and FIG. 4, floating gate electrode films 31 (secondelectrode films) that are made of, for example, polysilicon are providedbetween the silicon pillars 20 and the control gate electrode films 21.Because the floating gate electrode films 31 are provided at eachintersection between the silicon pillars 20 and the control gateelectrode films 21, the floating gate electrode films 31 are arranged ina matrix configuration to be separated from each other along theY-direction and the Z-direction. When viewed from the Z-direction, theconfiguration of the floating gate electrode film 31 is a fan-like shapethat is wider on the control gate electrode film 21 side. Therefore, alength L1 in the Y-direction of the end portion of the floating gateelectrode film 31 on the silicon pillar 20 side is shorter than a lengthL2 in the Y-direction of the end portion of the floating gate electrodefilm 31 on the control gate electrode film 21 side.

A tunneling insulating film 33 that is made of, for example, siliconoxide is provided between the silicon pillar 20 and the floating gateelectrode films 31. The tunneling insulating film 33 is provided at eachsilicon pillar 20; and the configuration of the tunneling insulatingfilm 33 is a band configuration that extends in the Z-direction and hasthe X-direction as the thickness direction and the Y-direction as thewidth direction.

On the other hand, a blocking insulating film 34 is provided between thefloating gate electrode film 31 and the control gate electrode film 21.The blocking insulating film 34 is, for example, a three-layer film inwhich a silicon nitride layer 35, a silicon oxide layer 36, and asilicon nitride layer 37 are stacked in this order from the floatinggate electrode film 31 side toward the control gate electrode film 21side. The silicon nitride layer 35 is formed around the floating gateelectrode film 31 to cover an upper surface 31 a and a lower surface 31b of the floating gate electrode film 31. The silicon oxide layer 36 andthe silicon nitride layer 37 are formed around the control gateelectrode film 21 to cover an upper surface 21 a and a lower surface 21b of the control gate electrode film 21.

Although the tunneling insulating film 33 normally is insulative, thetunneling insulating film 33 is a film in which a tunneling currentflows when a voltage within the range of the drive voltage of thesemiconductor memory device 1 is applied. The blocking insulating film34 is a film in which a current substantially does not flow even when avoltage within the range of the drive voltage of the semiconductormemory device 1 is applied. The equivalent oxide thickness (EOT) of thetunneling insulating film 33 is thicker than the equivalent oxidethickness of the blocking insulating film 34; and the dielectricconstant of the tunneling insulating film 33 is lower than thedielectric constant of the blocking insulating film.

In the peripheral circuit region Rc as shown in FIG. 2, a source region40 s and a drain region 40 d are formed in the silicon substrate 10 tobe separated from each other. The region between the source region 40 sand the drain region 40 d is a channel region 40 c. A gate insulatingfilm 41 (a fourth insulating film) that is made of, for example, siliconoxide is provided on the silicon substrate 10 in the region directlyabove the channel region 40 c; and a conductive layer 42 that is madeof, for example, polysilicon and an interconnect layer 43 that is madeof, for example, tungsten are stacked in this order on the gateinsulating film 41. A gate electrode 45 is formed of the conductivelayer 42 and the interconnect layer 43. A transistor 46 includes thesource region 40 s, the drain region 40 d, the channel region 40 c, thegate insulating film 41, and the gate electrode 45. The transistor 46 isincluded in the peripheral circuit.

As described below, the insulating film 11 that is in the memory cellregion Rm and the gate insulating film 41 that is in the peripheralcircuit region Rc are formed by dividing the same silicon oxide film;the conductive layer 12 that is in the memory cell region Rm and theconductive layer 42 that is in the peripheral circuit region Rc areformed by dividing the same polysilicon layer; and the interconnectlayer 13 that is in the memory cell region Rm and the interconnect layer43 that is in the peripheral circuit region Rc are formed by dividingthe same tungsten layer.

A method for manufacturing the semiconductor memory device according tothe embodiment will now be described.

FIG. 5A to FIG. 17B are plan views and cross-sectional views showing themethod for manufacturing the semiconductor memory device according tothe embodiment.

Only the memory cell region Rm is shown in FIG. 5A to FIG. 17B.

First, as shown in FIG. 1 and FIG. 2, the channel region 40 c, thesource region 40 s, and the drain region 40 d are formed in the upperlayer portion of the silicon substrate 10 in the peripheral circuitregion Rc. Then, a silicon oxide film is formed on the silicon substrate10 in both the memory cell region Rm and the peripheral circuit regionRc. Therefore, in the peripheral circuit region Rc, a relatively thinsilicon oxide film is formed in the low breakdown voltage transistor (LVTr) region; and a relatively thick silicon oxide film is formed in thehigh breakdown voltage transistor (HV Tr) region. Also, a relativelythick silicon oxide film is formed in the memory cell region Rm.

Then, a polysilicon layer is formed on the entire surface. STI (ShallowTrench Isolation) is formed in the upper layer portion of the siliconsubstrate 10 in the peripheral circuit region Rc using an appropriatemask (not shown). Then, a tungsten layer is formed. Then, a polysiliconlayer and a silicon oxide film are formed only in the memory cell regionRm. Then, these layers are patterned by RIE (Reactive Ion Etching).

Thereby, the insulating film 11, the conductive layer 12, theinterconnect layer 13, the conductive layer 14, and the insulating film17 are formed for each block in the memory cell region Rm. The cellsource line 15 is formed of the stacked body made of the conductivelayer 12, the interconnect layer 13, and the conductive layer 14.Erasing is possible by block unit by forming the cell source line 15 tobe divided for each block. On the other hand, the gate insulating film41, the conductive layer 42, and the interconnect layer 43 are formed inthe peripheral circuit region Rc. The gate electrode 45 is formed of thestacked body made of the conductive layer 42 and the interconnect layer43. Thereby, the transistor 46 is formed in the peripheral circuitregion Rc.

Then, as shown in FIGS. 5A and 5B, a silicon oxide film 51 and a siliconnitride film 52 are stacked alternately on the insulating film 17(referring to FIG. 2) in the memory cell region Rm. Thereby, the stackedbody 25 is formed. At this time, because the gate length (the totalthickness of the control gate electrode film 21 and the blockinginsulating film provided around the control gate electrode film 21) onthe electrode side is longer than the gate length (the total thicknessof the floating gate electrode film 31 and the blocking insulating filmprovided around the floating gate electrode film 31) on the channelside, the film thickness ratio of the silicon oxide film 51 and thesilicon nitride film 52 that are stacked is adjusted according to thefilm thickness of the blocking films filled from both sides. FIG. 5A isa cross-sectional view; and FIG. 5B is a top view. This is similar forthe following drawings as well.

Continuing as shown in FIGS. 6A and 6B, the hard mask 26 that is madeof, for example, silicon nitride is formed on the stacked body 25. Then,the hard mask 26 is patterned; and anisotropic etching such as RIE,etc., of the stacked body 25 is performed using the patterned hard mask26 as a mask. Thereby, multiple trenches 53 are made in the stacked body25 to extend in the Y-direction. The trenches 53 pierce the stacked body25.

Then, as shown in FIGS. 7A and 7B, the silicon nitride films 52 arerecessed by performing wet etching via the trench 53. Thereby, theexposed surfaces of the silicon nitride films 52 recede at the innersurface of the trench 53 to make recesses 54 that extend in theY-direction. Then, oxidation treatment is performed by SPA, etc.Thereby, the exposed surfaces of the silicon nitride films 52 at theinner surface of the trench 53 are covered with a thin silicon oxidelayer 50.

Continuing as shown in FIGS. 8A and 8B, the silicon nitride layer 35 isformed on the entire surface. Then, a polysilicon film 55 is formed onthe entire surface. The silicon nitride layer 35 and the polysiliconfilm 55 also are formed on the inner surface of the trench 53 to enterthe recesses 54.

Then, as shown in FIGS. 9A and 9B, by performing anisotropic etchingsuch as RIE, etc., along the trench 53, the polysilicon film 55 and thesilicon nitride layer 35 are selectively removed to remain inside therecesses 54; and the polysilicon films 55 that remain inside therecesses 54 adjacent to each other in the Z-direction are separated fromeach other. Similarly, the silicon nitride layers 35 that remain insidethe recesses 54 adjacent to each other in the Z-direction also areseparated from each other.

Continuing as shown in FIGS. 10A and 10B, the tunneling insulating film33, a polysilicon film 56, and an insulating film 57 are deposited inthis order.

Then, as shown in FIGS. 11A and 11B, trenches 58 are made in the stackedbody 25 and the stacked body stacked above the stacked body 25 to extendin the Y-direction between the trenches 53. Thereby, the trenches 53 andthe trenches 58 are arranged alternately along the X-direction.

Continuing as shown in FIGS. 12A and 12B, the silicon nitride films 52are recessed by performing wet etching using hot phosphoric acid via thetrench 58. The recessing is stopped by the silicon oxide layer 50 thatis exposed at the back surfaces of recesses 59. Thereby, the siliconnitride films 52 are removed; and the recesses 59 are made in the innersurface of the trench 58 to extend in the Y-direction. At this time, thesilicon nitride layer 35 is not damaged because the silicon nitridelayer 35 is protected by the silicon oxide layer 50.

Then, as shown in FIGS. 13A and 13B, the silicon oxide layer 50 that isexposed at the back surfaces of the recesses 59 is removed. Thereby, thesilicon nitride layers 35 are exposed at the back surfaces of therecesses 59. Then, the silicon oxide layer 36 and the silicon nitridelayer 37 are formed on the inner surface of the trench 58. As a result,as shown in FIG. 3, the blocking insulating film 34 is formed of thesilicon nitride layer 35, the silicon oxide layer 36, and the siliconnitride layer 37. Then, a tungsten film 61 is formed on the entiresurface by, for example, CVD (Chemical Vapor Deposition). The siliconoxide layer 36, the silicon nitride layer 37, and the tungsten film 61also enter the recesses 59 via the trench 58.

Continuing as shown in FIGS. 14A and 14B, the tungsten film 61 isselectively removed by performing anisotropic etching such as RIE, etc.Thereby, the tungsten film 61 is caused to remain inside the recesses59; and the tungsten films 61 that remain inside the recesses 59adjacent to each other in the Z-direction are separated from each other.As a result, the control gate electrode films 21 that are made of thetungsten films 61 are formed inside the recesses 59. Subsequently, theinter-layer insulating film 24 is filled into the trench 58; and theupper surface of the inter-layer insulating film 24 is planarized. FIG.14B is a cross-sectional view along line B-B′ shown in FIG. 14A.

Then, as shown in FIGS. 15A to 15C, a hard mask 62 is formed in whichopenings 62 a are arranged in a matrix configuration along theX-direction and the Y-direction. The configuration of each of theopenings 62 a is a rectangle with the X-direction as the longitudinaldirection; and the openings 62 a are arranged intermittently along theY-direction in the region directly above the polysilicon films 56 andthe insulating film 57 between the polysilicon films 56 but are notdisposed in the region directly above the inter-layer insulating film24. Then, the polysilicon film 56 and the insulating film 57 are dividedalong the Y-direction by performing anisotropic etching such as RIE,etc., using the hard mask 62 and the hard mask 26 as a mask. Thereby, athrough-hole 63 is made in the polysilicon film 56 and the insulatingfilm 57 in the region directly under the opening 62 a; the portion ofthe polysilicon film 56 that is formed on the hard mask 26 becomes theinterconnect 27; and the portion of the polysilicon film 56 that isdivided by the through-hole 63 becomes the silicon pillar 20. FIG. 15Bis a plan view along line C-C′ shown in FIG. 15A; and FIG. 15C is across-sectional view along line B-B′ shown in FIG. 15A.

Continuing as shown in FIG. 16, the tunneling insulating film 33 and thepolysilicon films 55 are selectively removed by performing isotropicetching such as CDE (Chemical Dry Etching), wet etching, etc., via thethrough-hole 63. Thereby, the tunneling insulating film 33 and thepolysilicon films 55 are divided along the Y-direction. The insulatingfilm 57 also is removed. As a result, the floating gate electrode films31 are formed of the polysilicon films 55. At this time, because thepolysilicon films 55 are etched from the silicon pillar 20 side, thelength L1 in the Y-direction of the end portion of the floating gateelectrode film 31 on the silicon pillar 20 side is shorter than thelength L2 in the Y-direction of the end portion of the floating gateelectrode film 31 on the control gate electrode film 21 side. On theother hand, at this time, the inter-layer insulating film 24 remainswithout being removed.

Then, as shown in FIGS. 17A and 17B, the inter-layer insulating film 23is deposited on the entire surface. The inter-layer insulating film 23is filled also inside the through-hole 63. The silicon oxide film 51also becomes a portion of the inter-layer insulating film 23.

Continuing as shown in FIG. 1 and FIG. 2, the vias 28, the vias 38, thebit lines 29, and the word lines 39 are formed. Thus, the semiconductormemory device 1 according to the embodiment is manufactured.

Effects of the embodiment will now be described.

In the embodiment, the floating gate electrode films 31 that are made ofpolysilicon are provided as charge storage units. Therefore, the dataretention characteristics of the memory cells are good; and the erasingoperation is fast because the charge that is stored in the floating gateelectrode films 31 can be erased by moving electrons instead of holes.The data retention characteristics are even better because the floatinggate electrode films 31 are separated from each other.

In the embodiment, because the blocking insulating film 34 is athree-layer film made of the silicon nitride layer 35, the silicon oxidelayer 36, and the silicon nitride layer 37, the coupling ratio can beensured while suppressing the leakage current. Also, the silicon nitridelayer 35 is formed from the silicon pillar 20 side in the process shownin FIGS. 8A and 8B; and the silicon oxide layer 36 and the siliconnitride layer 37 are formed from the control gate electrode film 21 sidein the process shown in FIGS. 13A and 13B.

Thus, by dividing the three-layer film of the blocking insulating film34 into two and forming the three-layer film from both sides, comparedto the case of forming from only one side, the thickness of the blockinginsulating film 34 can be distributed on the two X-direction sides ofthe floating gate electrode film 31; and the thickness in theZ-direction as an entirety can be reduced. Thereby, the height in theZ-direction of the recesses 54 (referring to FIGS. 8A and 8B) and therecesses 59 (referring to FIGS. 13A and 13B) can be reduced; the bitdensity of the memory cells in the Z-direction can be increased; and theaspect ratio can be reduced.

In the embodiment, the blocking insulating film 34 is divided for eachof the control gate electrode films 21 along the Z-direction. Thereby,the electrons that are stored in the floating gate electrode film 31 canbe prevented from propagating through the blocking insulating film 34and leaking. As a result, the data retention characteristics of thememory cells are good.

In the embodiment, as shown in FIG. 4, the configuration of the floatinggate electrode film 31 is a fan-like shape that is wider on the controlgate electrode film 21 side. Thereby, the IPD capacitance between thefloating gate electrode film 31 and the control gate electrode film 21can be large; and the coupling ratio can be large.

Although an example is illustrated in the embodiment in which theblocking insulating film 34 is a three-layer film, this is not limitedthereto. The layers of the blocking insulating film 34 are not limitedto the silicon oxide layer (the SiO₂ layer) and the silicon nitridelayers (the Si₃N₄ layers) and may be a high dielectric constant layersuch as, for example, an Al₂O₃ layer, a MgO layer, a SrO layer, a SiNlayer, a BaO layer, a TiO layer, a Ta₂O₅ layer, a BaTiO₃ layer, a BaZrOlayer, a ZrO₂ layer, a Y₂O₃ layer, a ZrSiO layer, a HfAlO layer, a HfSiOlayer, a La₂O₃ layer, a LaAlO layer, etc.

Although an example is illustrated in the embodiment in which thefloating gate electrode film 31 is formed of polysilicon, the floatinggate electrode film 31 is not limited thereto and may be formed of, forexample, a metal silicide or a metal.

Although an example is illustrated in the embodiment in which thecontrol gate electrode film 21 is formed of tungsten, the control gateelectrode film 21 is not limited thereto and may be formed of, forexample, a metal silicide by filling a polysilicon film and subsequentlysiliciding the polysilicon film.

In the process shown in FIGS. 5A and 5B, the silicon nitride films 52 ofthe lowermost layer and the uppermost layer may be formed to be thickerthan the other silicon nitride films 52. Thereby, the film thicknessesof the selection gate electrode films that are formed below and abovethe control gate electrode films 21 can be thicker than those of thecontrol gate electrode films 21. As a result, a selection transistorthat has a gate length longer than that of the memory cell transistorcan be formed.

Several layers of the control gate electrode films 21 provided at theupper portion of the stacked body 25 may be shorted to each other to beused as the selection gate electrode film; and several layers of thecontrol gate electrode films 21 provided at the lower portion of thestacked body 25 may be shorted to each other to be used as the selectiongate electrode film. Thereby, a selection transistor that has a gatelength longer than that of the memory cell transistor can be formed.

Modification of First Embodiment

A modification of the embodiment will now be described.

FIG. 18 is a cross-sectional view showing a semiconductor memory deviceaccording to the modification.

In the semiconductor memory device is according to the modification asshown in FIG. 18, one wide silicon pillar 65 is provided between twofloating gate electrode films 31 adjacent to each other in theX-direction. In other words, the inter-layer insulating film 24 is notprovided between the two silicon pillars 20 belonging to each of thesets 22; and the two silicon pillars 20 are formed as one body.

In the semiconductor memory device is according to the modification, thetwo X-direction side portions of the wide silicon pillar 65 are used asdistinct channels. Otherwise, the configuration, the manufacturingmethod, and the effects of the modification are similar to those of thefirst embodiment described above.

Second Embodiment

A second embodiment will now be described.

FIG. 19 is a cross-sectional view showing a semiconductor memory deviceaccording to the embodiment.

As shown in FIG. 19, the semiconductor memory device 2 according to theembodiment differs from the semiconductor memory device 1 (referring toFIG. 1 to FIG. 4) according to the first embodiment described above inthat the disposition of the tunneling insulating film 33 and theblocking insulating film 34 is reversed.

In other words, in the semiconductor memory device 2, the blockinginsulating film 34 is disposed between the silicon pillar 20 and thefloating gate electrode films 31; and the tunneling insulating film 33is disposed between the floating gate electrode films 31 and the controlgate electrode films 21.

Therefore, the components included in the memory cell are arranged inthe order of silicon pillar 20-blocking insulating film 34-floating gateelectrode film 31-tunneling insulating film 33-control gate electrodefilm 21.

More specifically, in the semiconductor memory device 2, silicon oxidefilms 71 are arranged to be separated from each other along theZ-direction; and the floating gate electrode films 31 and the controlgate electrode films 21 are provided in the spaces between themutually-adjacent silicon oxide films 71. Also, the tunneling insulatingfilm 33 is disposed to cover the upper surface and the lower surface ofthe control gate electrode film 21 and the side surface of the controlgate electrode film 21 on the floating gate electrode film 31 side. Onthe other hand, the blocking insulating film 34 is disposed linearlyalong the side surface of the silicon pillar 20.

Similarly to the first embodiment, the blocking insulating film 34 maybe a multilayered film, e.g., a three-layer film. However, the blockinginsulating film 34 is not subdivided between the silicon pillar 20 sideand the control gate electrode film 21 side; and the entire blockinginsulating film 34 is disposed on the silicon pillar 20 side.

In the semiconductor memory device 2, the lower end portions of the twosilicon pillars 20 belonging to the set 22 are connected to each other;and the cell source line 15 is not provided. A source line (not shown)is provided above the stacked body. In other words, the semiconductormemory device 2 is a U-shaped pillar type stacked memory device.Otherwise, the configuration of the embodiment is similar to that of thefirst embodiment described above.

The basic operations and the read-out method of the semiconductor memorydevice 2 are similar to those of a normal NAND flash memory; and thepolarity of the voltage applied between the silicon pillar 20 and thecontrol gate electrode film 21 in the programming operation and theerasing operation are the reverse of those of a normal NAND flashmemory. Thereby, the charge is caused to move into and out of thesilicon pillar 20 from the control gate electrode film 21.

A method for manufacturing the semiconductor memory device according tothe embodiment will now be described.

FIG. 20A to FIG. 30C are plan views and cross-sectional views showingthe method for manufacturing the semiconductor memory device accordingto the embodiment.

First, as shown in FIGS. 20A and 20B, the insulating film 17 that ismade of silicon oxide is formed on the silicon substrate 10 (referringto FIG. 2); and subsequently, a stacked body 73 is formed by alternatelystacking the silicon oxide film 71 and a polysilicon film 72. Thepolysilicon film 72 may be doped with boron (B), may be doped withphosphorus (P), or may not be doped. FIG. 20A is a cross-sectional view;and FIG. 20B is a top view. This is similar for the following drawingsas well.

Then, as shown in FIGS. 21A and 21B, multiple trenches 75 are made inthe stacked body 73 to extend in the Y-direction by forming a hard mask(not shown) on the stacked body 73, patterning by lithography, andperforming anisotropic etching such as RIE, etc., using the patternedhard mask as a mask. The trenches 75 pierce the stacked body 73 in theZ-direction but do not pierce the insulating film 17.

Continuing as shown in FIGS. 22A and 22B, on the inner surface of thetrench 75, the blocking insulating film 34 is formed; and subsequently,a polysilicon film 77 is formed. The blocking insulating film 34 and thepolysilicon film 77 are formed on the side surface of the trench 75 andon the bottom surface of the trench 75 to be folded back into a U-shapedas viewed from the Y-direction. Accordingly, the relationship betweenthe width of the trench 75 and the film thicknesses of the blockinginsulating film 34 and the polysilicon film 77 is set such that suchfolding back is possible. Then, the inter-layer insulating film 24 isfilled into the trench 75 by depositing silicon oxide.

Then, as shown in FIGS. 23A and 23B, trenches 78 are made in the portionof the stacked body 73 between the trenches 75 to extend in theY-direction by forming a hard mask (not shown) on the stacked body 73,patterning by lithography, and performing anisotropic etching such asRIE, etc., using the patterned hard mask as a mask. The trenches 75 andthe trenches 78 are arranged alternately along the X-direction.

Continuing as shown in FIGS. 24A and 24B, wet etching is performedusing, for example, TMY (choline aqueous solution). Thereby, thepolysilicon films 72 are etched isotropically via the trench 78; and theexposed surfaces of the polysilicon films 72 at the inner surface of thetrench 78 are caused to recede. Thereby, recesses 79 are made at theinner surface of the trench 78.

Then, as shown in FIGS. 25A and 25B, the tunneling insulating film 33 isformed by depositing silicon oxide on the inner surface of the trench78. At this time, the tunneling insulating film 33 is formed also on theinner surfaces of the recesses 79 to contact the polysilicon films 72.The tunneling insulating film 33 may be formed by thermal oxidation ofthe exposed surfaces of the polysilicon films 72.

Continuing as shown in FIGS. 26A and 26B, a tungsten film 81 is formedinside the trench 78 by, for example, depositing tungsten by CVD. Atthis time, the tungsten film 81 is filled also into the recesses 79.

Then, as shown in FIGS. 27A and 27B, the portion of the tungsten film 81that is not filled into the recesses 79 is removed by etching thetungsten film 81. Thereby, the tungsten films 81 that remain inside therecesses 79 are separated from each other between the recesses 79 tobecome the control gate electrode films 21. Then, the inter-layerinsulating film 24 is filled into the trench 78; and the upper surfaceof the inter-layer insulating film 24 is planarized. Instead oftungsten, silicon may be deposited in the process shown in FIGS. 26A and26B; and the silicon may be silicided in this process. Thereby, thecontrol gate electrode films 21 are formed of a metal silicide.

Continuing as shown in FIGS. 28A to 28C, through-holes 82 are made inthe trench 75 by selectively removing the inter-layer insulating film24, the polysilicon film 77, and the blocking insulating film 34 byperforming anisotropic etching using an appropriate mask. Thepolysilicon film 77 is divided periodically along the Y-direction by thethrough-holes 82 to become the silicon pillars 20. FIG. 28A is across-sectional view; FIG. 28B is a cross-sectional view along line C-C′shown in FIG. 28A; and FIG. 28C is a cross-sectional view along lineB-B′ shown in FIG. 28A. This is similar for FIGS. 29A to 29C and FIGS.30A to 30C.

Then, as shown in FIGS. 29A to 29C, the blocking insulating film 34, thepolysilicon films 72, and the tunneling insulating film 33 are furtherremoved via the through-holes 82 to be divided along the Y-direction byperforming isotropic etching such as CDE, wet etching, etc. Thereby, thepolysilicon films 72 that are divided along the Y-direction become thefloating gate electrode films 31. At this time, the configuration of thefloating gate electrode film 31 becomes a fan-like shape that is wideron the control gate electrode film 21 side according to the conditionsof the isotropic etching.

Continuing as shown in FIGS. 30A to 30C, the inter-layer insulating film24 is filled into the through-holes 82 by, for example, depositingsilicon oxide and planarizing the upper surface of the silicon oxide.Then, the vias 28, the vias 38, the source lines, the bit lines 29, andthe word lines 39 (referring to FIG. 1 and FIG. 2) are formed by normalmethods. Thus, the semiconductor memory device 2 according to theembodiment is manufactured.

Effects of the embodiment will now be described.

In the programming operation and the erasing operation of a NAND memorydevice, it is necessary for the current to flow in the tunnelinginsulating film and for the current to not flow easily in the blockinginsulating film. To this end, it is necessary for the physical filmthickness of the blocking insulating film to be thicker than thephysical film thickness of the tunneling insulating film. Accordingly,if the blocking insulating film 34 is to be formed to extend around intothe gaps between the silicon oxide films 71, it is necessary to set thespacing between the silicon oxide films 71 to be long in theZ-direction, which obstructs higher integration of the memory cells inthe Z-direction. Further, the aspect ratio of the trenches 75 and 78undesirably increases; and patterning becomes difficult.

If the spacing of the silicon oxide films 71 nevertheless is set to beshort, the thickness of the control gate electrode film 21, which iscovered with the blocking insulating film 34 at the upper surface andthe lower surface of the control gate electrode film 21, becomes shorterthan the spacing of the silicon oxide films 71. Accordingly, theinterconnect resistance of the control gate electrode film 21 increases;the gate length of the memory cell transistor becomes short; and thecharacteristics of the memory cell transistor undesirably degrade due tothe short channel effect.

Conversely, in the embodiment, the blocking insulating film 34 is formedon the inner surface of the trench 75 in the process shown in FIGS. 22Aand 22B. Thus, by forming the blocking insulating film 34 at an earlystage, it is no longer necessary for the blocking insulating film 34 toextend around into the gaps between the silicon oxide films 71; and thespacing of the silicon oxide films 71 can be shorter. As shown in FIG.19, in the embodiment, although the tunneling insulating film 33 extendsaround into the gaps between the silicon oxide films 71, there are fewproblems because the tunneling insulating film 33 is thinner than theblocking insulating film 34 as described above. Thus, according to theembodiment, the bit density of the memory cells in the Z-direction canbe increased after ensuring the thickness of the control gate electrodefilm 21; and the aspect ratio can be reduced. Otherwise, the effects ofthe embodiment are similar to those of the first embodiment describedabove.

First Modification of Second Embodiment

A first modification of the embodiment will now be described.

FIG. 31 is a cross-sectional view showing a semiconductor memory deviceaccording to the modification. In the semiconductor memory device 2 aaccording to the modification as shown in FIG. 31, a charge storage film85 that is made of an insulative charge storage material is providedinstead of the floating gate electrode film 31 that is made of aconductive material. The charge storage film 85 is formed of, forexample, silicon nitride. Accordingly, the memory cell of thesemiconductor memory device 2 a has a MONOS structure. Otherwise, theconfiguration, the manufacturing method, the operations, and the effectsof the modification are similar to those of the second embodimentdescribed above.

Second Modification of Second Embodiment

A second modification of the embodiment will now be described.

FIG. 32 is a cross-sectional view showing a semiconductor memory deviceaccording to the modification.

In the semiconductor memory device 2 b according to the modification asshown in FIG. 32, the cell source line 15 is provided; and the lower endof the silicon pillar 20 is connected to the cell source line 15. Inother words, the semiconductor memory device 2 b is an I-shaped pillartype stacked memory device.

To connect the lower end of the silicon pillar 20 to the cell sourceline 15 when manufacturing the semiconductor memory device 2 b accordingto the modification, it is necessary for the portion of the blockinginsulating film 34 formed on the bottom surface of the trench 75 to beremoved by etching in the process shown in FIGS. 22A and 22B. However,the etching does not damage the tunneling insulating film 33 because thetunneling insulating film 33 is not yet formed at this time. Otherwise,the configuration, the manufacturing method, the operations, and theeffects of the modification are similar to those of the secondembodiment described above.

Third Modification of Second Embodiment

A third modification of the embodiment will now be described.

FIG. 33 is a cross-sectional view showing a semiconductor memory deviceaccording to the modification.

As shown in FIG. 33, the modification is an example in which the firstmodification and the second modification described above are combined.Namely, in the semiconductor memory device 2 c according to themodification, the charge storage film 85 that is made of an insulativecharge storage material is provided; and the lower end of the siliconpillar 20 is connected to the cell source line 15. Accordingly, thesemiconductor memory device 2 c has a MONOS structure and is theI-shaped pillar type. Otherwise, the configuration, the manufacturingmethod, the operations, and the effects of the modification are similarto those of the second embodiment and the first and second modificationsof the second embodiment described above.

Third Embodiment

A third embodiment will now be described.

FIG. 34 is a cross-sectional view showing a semiconductor memory deviceaccording to the embodiment.

Compared to the semiconductor memory device 2 (referring to FIG. 19)according to the second embodiment described above, in the semiconductormemory device 3 according to the embodiment as shown in FIG. 34, an airgap 86 is made between the silicon pillars 20, the control gateelectrode films 21, the floating gate electrode films 31, the tunnelinginsulating films 33, and the blocking insulating films 34. Morespecifically, the air gap 86 is made between the control gate electrodefilms 21 adjacent to each other in the Z-direction, between the floatinggate electrode films 31 adjacent to each other in the Z-direction,between the silicon pillars 20 adjacent to each other in theY-direction, between the blocking insulating films 34, between thefloating gate electrode films 31, between the tunneling insulating films33, and between the two silicon pillars 20 adjacent to each other in theX-direction and belonging to the same set 22.

A method for manufacturing the semiconductor memory device according tothe embodiment will now be described.

FIGS. 35A and 35B to FIGS. 37A to 37C are plan views and cross-sectionalviews showing the method for manufacturing the semiconductor memorydevice according to the embodiment.

FIG. 35A is a cross-sectional view; and FIG. 35B is a plan view. FIG.36A is a cross-sectional view; FIG. 36B is a cross-sectional view alongline C-C′ shown in FIG. 36A; and FIG. 36C is a cross-sectional viewalong line B-B′ shown in FIG. 36A. This is similar for FIGS. 37A to 37C.

First, as shown in FIGS. 35A and 35B, a stacked body is formed byforming the insulating film 17 made of silicon oxide on the siliconsubstrate 10 (referring to FIG. 2) and subsequently stacking a siliconnitride film 87 alternately with the polysilicon film 72.

Then, the processes shown in FIGS. 21A and 21B to FIGS. 29A to 29C areimplemented. However, in the processes shown in FIGS. 24A and 24B andFIGS. 27A and 27B, a silicon nitride film 88 is filled instead of theinter-layer insulating film 24 made of silicon oxide.

Thereby, as shown in FIGS. 36A to 36C, an intermediate structural bodythat is similar to the intermediate structural body shown in FIGS. 29Ato 29C is made. However, in the intermediate structural body of theembodiment, the silicon nitride films 87 are provided instead of thesilicon oxide films 71; and the silicon nitride film 88 is providedinstead of the inter-layer insulating film 24.

Then, as shown in FIGS. 37A to 37C, the silicon nitride films 87 and thesilicon nitride film 88 are removed by, for example, wet etching.Thereby, the air gap 86 is made in the space where the silicon nitridefilms 87 and the silicon nitride film 88 were disposed. Thus, thesemiconductor memory device 3 according to the embodiment ismanufactured.

According to the embodiment, because the air gap 86 is made between thesilicon pillars 20, the control gate electrode films 21, the floatinggate electrode films 31, the tunneling insulating films 33, and theblocking insulating films 34, the proximity effect can be suppressed;and the breakdown voltage can be increased.

Otherwise, the configuration, the manufacturing method, the operations,and the effects of the embodiment are similar to those of the secondembodiment described above.

It is possible for the air gap to be made only between the siliconpillars 20 by alternately stacking the silicon oxide film 71 and thepolysilicon film 72 instead of the silicon nitride film 87 and thepolysilicon film 72 in the process shown in FIGS. 35A and 35B.

Modification of Third Embodiment

A modification of the embodiment will now be described.

FIGS. 38A to 38C are cross-sectional views showing a semiconductormemory device according to the modification.

FIG. 38A is a cross-sectional view; FIG. 38B is a cross-sectional viewalong line C-C′ shown in FIG. 38A; and FIG. 38C is a cross-sectionalview along line B-B′ shown in FIG. 38A.

FIG. 38A is a cross-sectional view along line D-D′ shown in FIG. 38C.This is similar for FIGS. 39A to 39C described below.

As shown in FIGS. 38A to 38C, the semiconductor memory device 3 aaccording to the modification differs from the semiconductor memorydevice 3 (referring to FIG. 34) according to the third embodimentdescribed above in that a reinforcing member 89 is formed in multipleregions by causing the silicon nitride films 87 and 88 to partiallyremain. The reinforcing member 89 extends in the Z-direction and isdisposed intermittently along the Y-direction inside the semiconductormemory device 3 a.

FIGS. 39A to 39C are cross-sectional views showing a method formanufacturing the semiconductor memory device according to themodification.

In the modification as shown in FIGS. 39A to 39C, the through-holes 82are not made in the region where the reinforcing member 89 is to beformed. Thereby, in the process shown in FIGS. 37A to 37C, the siliconnitride films 87 and 88 remain locally to become the reinforcing member89 when performing wet etching of the silicon nitride films 87 and 88via the through-holes 82.

According to the modification, by providing the reinforcing member 89,the mechanical strength of the semiconductor memory device 3 a can beensured; and collapse can be prevented. Otherwise, the configuration,the manufacturing method, the operations, and the effects of themodification are similar to those of the third embodiment describedabove.

Fourth Embodiment

A fourth embodiment will now be described.

FIG. 40 is a cross-sectional view showing a semiconductor memory deviceaccording to the embodiment.

FIG. 41 is a cross-sectional view showing region E shown in FIG. 40.

As shown in FIG. 40 and FIG. 41, the semiconductor memory device 4according to the embodiment differs from the semiconductor memory device1 (referring to FIG. 1 to FIG. 4) according to the first embodimentdescribed above in that the blocking insulating film 34 is not disposedbetween a control gate electrode film 21 u of the uppermost level and afloating gate electrode film 31 u of the uppermost level; and thecontrol gate electrode film 21 u of the uppermost level is connected tothe floating gate electrode film 31 u of the uppermost level.

The semiconductor memory device according to the embodiment will now bedescribed.

FIG. 42A is a cross-sectional view showing a method for manufacturingthe semiconductor memory device according to the embodiment; and FIG.42B is a plan view.

First, the processes shown in FIGS. 5A and 5B to FIGS. 12A and 12B areimplemented.

Then, as shown in FIGS. 42A and 42B, the silicon oxide layer 36 and thesilicon nitride layer 37 are formed on the inner surface of the trench58. Then, a resist material 90 is filled into the trench 58; and arecess 59 u of the uppermost level is exposed by the upper surface ofthe resist material 90 being recessed. Then, the portions of the siliconnitride layer 37, the silicon oxide layer 36, and the silicon nitridelayer 35 that are exposed from the resist material 90 are removed by,for example, wet etching. Thereby, the polysilicon film 55 is exposed atthe back surface of the recess 59 u of the uppermost level. Then, theresist material 90 is removed.

Continuing as shown in FIGS. 13A and 13B, the tungsten film 61 is formedon the inner surface of the trench 58. At this time, the tungsten film61 contacts the polysilicon film 55 inside the recess 59 u of theuppermost level. The subsequent processes are similar to those of thefirst embodiment described above.

According to the embodiment, the control gate electrode film 21 u of theuppermost level and the floating gate electrode film 31 u of theuppermost level can be electrically integrated to be used as theselection gate electrode film by causing the control gate electrode film21 u to connect the floating gate electrode film 31 u. Thereby, aselection gate transistor can be formed in which the threshold does notfluctuate because charge is not stored.

Otherwise, the configuration, the manufacturing method, the operations,and the effects of the embodiment are similar to those of the firstembodiment described above.

Fifth Embodiment

A fifth embodiment will now be described.

FIG. 43 and FIG. 44 are cross-sectional views showing a semiconductormemory device according to the embodiment.

In the semiconductor memory device 5 according to the embodiment asshown in FIG. 43 and FIG. 44, the multiple silicon pillars 20 areprovided and arranged in a matrix configuration along the X-directionand the Y-direction. Each of the silicon pillars 20 has a circularcolumnar configuration extending in the Z-direction. The tunnelinginsulating films 33, the floating gate electrode films 31, and theblocking insulating film 34 are provided in circular ring configurationsaround each of the silicon pillars 20 in order from the inside, i.e.,the silicon pillar 20 side. In other words, the floating gate electrodefilms 31 are provided around the silicon pillar 20 as viewed from theZ-direction.

The tunneling insulating films 33 and the floating gate electrode films31 are divided in the Z-direction. The silicon oxide films 51 areprovided between the stacked bodies having the circular ringconfigurations made of the tunneling insulating film 33 and the floatinggate electrode film 31 in the Z-direction. In the floating gateelectrode film 31, a polysilicon layer 91 is disposed on the inner side;and a metal silicide layer 92 is disposed on the outer side. The metalsilicide layer 92 is formed of a metal silicide but may be formed of ametal.

In the blocking insulating film 34, a silicon oxide layer 93 is disposedon the inner side; and high dielectric constant layers 94 are disposedon the outer side. The high dielectric constant layers 94 are made of amaterial having a higher dielectric constant than silicon oxide, forexample, hafnium (Hf), aluminum oxide (AlO), titanium nitride (TiN),tantalum nitride (TaN), or tantalum oxide (TaO). The silicon oxide layer93 is provided continuously in a tubular configuration in theZ-direction. However, the diameter of the tube fluctuates periodicallysuch that the diameter of the portions corresponding to the floatinggate electrode films 31 is relatively small and the diameter of theportions corresponding to the silicon oxide films 51 is relativelylarge. Therefore, the silicon oxide layer 93 has a circular tubularbellows-like configuration. The high dielectric constant layers 94 aredisposed inside recesses 93 a at the outer surface of the circulartubular bellows-like configuration made of the silicon oxide layer andare divided for each of the recesses 93 a. The configuration of theblocking insulating film 34 is not limited to the two-layer structuremade of the silicon oxide layer 93 and the high dielectric constantlayers 94. For example, the configuration may be a combination of anylayer of a silicon oxide layer (a SiO₂ layer), a silicon nitride layer(a Si₃N₄ layer), an Al₂O₃ layer, a MgO layer, a SrO layer, a SiN layer,a BaO layer, a TiO layer, a Ta₂O₅ layer, a BaTiO₃ layer, a BaZrO layer,a ZrO₂ layer, a Y₂O₃ layer, a ZrSiO layer, a HfAlO layer, a HfSiO layer,a La₂O₃ layer, a LaAlO layer, etc.

In the semiconductor memory device 5, the multiple control gateelectrode films 21 are provided to be arranged in a matrix configurationalong the X-direction and the Z-direction. The control gate electrodefilms 21 have band configurations extending in the Y-direction. Thecontrol gate electrode film 21 is a conductive film, e.g., a two-layerfilm made of a titanium nitride layer (TiN) and a tungsten layer (W), atwo-layer film made of a tungsten nitride layer (WN) and a tungstenlayer (W), or a two-layer film made of a tantalum nitride layer (TaN)and a tungsten layer (W). However, the configuration of the control gateelectrode film 21 is not limited thereto; and, for example, a metalsilicide layer formed by siliciding a polysilicon film may be used.

The structural body that is made of the silicon pillar 20, the tunnelinginsulating film 33, the floating gate electrode films 31, and theblocking insulating film 34 pierces the control gate electrode films 21.The control gate electrode films 21 are disposed in the recesses 93 a.In other words, the control gate electrode films 21 are provided aroundthe floating gate electrode films 31 as viewed from the Z-direction. Theinter-layer insulating film 24 is provided between the structural bodiesmade of the silicon pillar 20, the tunneling insulating film 33, thefloating gate electrode films 31, the blocking insulating film 34, andthe control gate electrode films 21.

A method for manufacturing the semiconductor memory device according tothe embodiment will now be described.

FIG. 45 to FIG. 53 are cross-sectional views showing the method formanufacturing the semiconductor memory device according to theembodiment.

First, similarly to the first embodiment described above, the insulatingfilm 11, the cell source line 15, and the insulating film 17 (referringto FIG. 1 and FIG. 2) are formed on the silicon substrate 10.

Then, as shown in FIG. 45, the stacked body 60 is formed by alternatelystacking the silicon oxide film 51 and the silicon nitride film 52.

Continuing, multiple memory holes 95 are made in the stacked body 60.The memory holes 95 extend in the Z-direction and pierce the stackedbody 60 and the insulating film 17 (referring to FIG. 2) to reach thecell source line 15.

Then, as shown in FIG. 46, the exposed surfaces of the silicon nitridefilms 52 at the inner surface of the memory hole 95 are caused to recedeby performing wet etching. Thereby, recesses 96 having annularconfigurations are made in the inner surface of the memory hole 95.

Continuing as shown in FIG. 47, the polysilicon layers 91 are filledinto the recess 96 by depositing polysilicon and selectively removingthe polysilicon by performing isotropic etching. Then, the tunnelinginsulating films 33 are formed by oxidizing the exposed surfaces of thepolysilicon layers 91.

Then, as shown in FIG. 48, the silicon pillar 20 is formed by fillingpolysilicon into the memory hole 95. The silicon pillar 20 is connectedto the cell source line 15 (referring to FIG. 2).

Continuing as shown in FIG. 49, a trench 97 is made in the portion ofthe stacked body 60 between the memory holes 95. The trench 97 spreadsin the Y-direction and the Z-direction, and pierces the stacked body 60in the Z-direction but does not pierce the insulating film 17 (referringto FIG. 2).

Then, as shown in FIG. 50, the silicon nitride films 52 are removed byperforming wet etching via the trench 97. Thereby, recesses 98 are madeat the inner surface of the trench 97. The polysilicon layers 91 areexposed at the back surfaces of the recesses 98.

Continuing as shown in FIG. 51, the exposed surfaces of the polysiliconlayers 91 inside the recesses 98 are silicided by siliciding via thetrench 97 and the recesses 98. Thereby, the metal silicide layers 92 areformed. The floating gate electrode film 31 includes the polysiliconlayer 91 and the metal silicide layer 92.

Then, as shown in FIG. 52, the silicon oxide layer 93 is formed on theinner surface of the trench 97. Then, the high dielectric constant layer94 is formed on the silicon oxide layer 93. The silicon oxide layer 93and the high dielectric constant layer 94 have circular tubularbellows-like configurations reflecting the recesses 98.

Continuing as shown in FIG. 53, a conductive film 99 is formed on thehigh dielectric constant layer 94 by depositing a conductive materialby, for example, CVD. The conductive film 99 also is filled into therecesses 98 but is formed such that the trench 97 is not filled.

Then, as shown in FIG. 43 and FIG. 44, the conductive film 99 and thehigh dielectric constant layer 94 are recessed by performing isotropicetching such that the conductive film 99 and the high dielectricconstant layer 94 remain only inside the recesses 93 a of the siliconoxide layer 93. Thereby, the conductive films 99 that remain inside therecesses 93 a become the control gate electrode films 21. Also, theblocking insulating film 34 is formed of the silicon oxide layer 93 andthe remaining portion of the high dielectric constant layer 94. Thus,the semiconductor memory device 5 according to the embodiment ismanufactured.

Effects of the embodiment will now be described.

According to the embodiment, memory cells having good controllabilitycan be realized because the control gate electrode films 21 are providedaround the floating gate electrode films 31 and the silicon pillar 20.

The programming characteristics are good because the floating gateelectrode films 31 are formed of conductors. Also, because the floatinggate electrode films 31 are separated from each other, the movement ofthe charge is suppressed; and the data retention characteristics arehigh. The erasing characteristics are good because the erasingoperations can be implemented by FN erasing or assisted erasing from thefloating gate electrode films 31.

In the embodiment, it is unnecessary to remove the tunneling insulatingfilm 33 formed on the bottom surface of the memory hole 95 by etchingbecause the silicon pillar 20 is connected to the cell source line 15(referring to FIG. 2) because the tunneling insulating film 33 is formedin the process shown in FIG. 47 prior to forming the silicon pillar 20in the process shown in FIG. 48. Therefore, the tunneling insulatingfilms that are formed on the side surface of the memory hole 95 are notdamaged by the etching.

Otherwise, the configuration, the manufacturing method, the operations,and the effects of the embodiment are similar to those of the firstembodiment described above. Although an I-shaped pillar type device isillustrated in the embodiment, a U-shaped pillar type device may be usedsimilarly to the first modification of the second embodiment describedabove.

Modification of Fifth Embodiment

A modification of the fifth embodiment will now be described.

FIG. 54 is a cross-sectional view showing a semiconductor memory deviceaccording to the modification.

As shown in FIG. 54, the modification is an example in which the fourthembodiment and the fifth embodiment described above are combined.Namely, the semiconductor memory device 5 a according to themodification differs from the semiconductor memory device 5 (referringto FIG. 43) according to the fifth embodiment described above in thatthe blocking insulating film 34 is not disposed between the control gateelectrode film 21 u of the uppermost level and the floating gateelectrode film 31 u of the uppermost level; and the control gateelectrode film 21 u of the uppermost level is connected to the floatinggate electrode film 31 u of the uppermost level. However, the level atwhich the control gate electrode film 21 is connected to the floatinggate electrode film 31 is not limited to the uppermost level and may bemultiple levels including the uppermost level.

A method for manufacturing the semiconductor memory device according tothe modification will now be described.

FIG. 55 to FIG. 57 are cross-sectional views showing the method formanufacturing the semiconductor memory device according to themodification.

First, the processes shown in FIG. 45 to FIG. 52 are implemented.

Then, as shown in FIG. 55, the resist material 90 is filled into thetrench 97 and recessed from the upper surface side by exposing. Thereby,the recess 93 a of the uppermost level is exposed from the resistmaterial 90. Although the recesses 93 a of multiple levels including theuppermost level may be exposed at this time, in the descriptionhereinbelow, an example is described in which only the recess 93 a ofthe uppermost level is exposed.

Continuing as shown in FIG. 56, the portions of the high dielectricconstant layer 94 and the silicon oxide layer 93 exposed from the resistmaterial 90 are removed by performing isotropic etching such as, forexample, wet etching, etc. Thereby, the metal silicide layer 92 isexposed at the back surface of the recess 93 a of the uppermost level.

Then, as shown in FIG. 57, the resist material 90 is removed.

Continuing, the process shown in FIG. 53 is implemented. Thus, thesemiconductor memory device 5 a according to the modification can bemanufactured.

According to the modification, similarly to the fourth embodimentdescribed above, the control gate electrode film 21 u and the floatinggate electrode film 31 u of the uppermost level can be electricallyintegrated to be used as the selection gate electrode film. As a result,a selection gate transistor can be formed in which the threshold doesnot fluctuate. Otherwise, the configuration, the manufacturing method,the operations, and the effects of the modification are similar to thoseof the fifth embodiment described above.

According to the embodiments described above, a semiconductor memorydevice having good data retention characteristics and a method formanufacturing the semiconductor memory device can be realized.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the invention. Additionally, the embodiments described abovecan be combined mutually.

What is claimed is:
 1. A semiconductor memory device, comprising: asubstrate; a semiconductor pillar provided on the substrate to extend ina vertical direction; a plurality of first electrode films providedsideward of the semiconductor pillar to extend in a first direction, theplurality of first electrode films being disposed to be separated fromeach other along the vertical direction; a plurality of second electrodefilms provided between the semiconductor pillar and the first electrodefilms, the plurality of second electrode films being disposed to beseparated from each other along the vertical direction; a firstinsulating film provided between the semiconductor pillar and the secondelectrode films; and a second insulating film provided between thesecond electrode film and the first electrode film.
 2. The deviceaccording to claim 1, wherein an equivalent oxide thickness of the firstinsulating film is thicker than an equivalent oxide thickness of thesecond insulating film, and a dielectric constant of the firstinsulating film is lower than a dielectric constant of the secondinsulating film.
 3. The device according to claim 2, wherein the secondinsulating film includes: a first layer provided on the first electrodefilm side to cover an upper surface and a lower surface of the firstelectrode film; and a second layer provided on the second electrode filmside to cover an upper surface and a lower surface of the secondelectrode film.
 4. The device according to claim 1, wherein anequivalent oxide thickness of the second insulating film is thicker thanan equivalent oxide thickness of the first insulating film, and adielectric constant of the second insulating film is lower than adielectric constant of the first insulating film.
 5. The deviceaccording to claim 4, wherein the first insulating film is disposedalong a side surface of the semiconductor pillar.
 6. The deviceaccording to claim 1, wherein a plurality of the semiconductor pillarsare provided, the plurality of semiconductor pillars is arranged in amatrix configuration along the first direction and a second directionintersecting the first direction as viewed from above, the firstelectrode film is not disposed between the semiconductor pillarsarranged along the first direction, and when the semiconductor pillarsarranged along the second direction are organized into sets every twomutually-adjacent semiconductor pillars and when two of the firstelectrode films are positioned between the sets, the first electrodefilms are not disposed between the two semiconductor pillars belongingto each set.
 7. The device according to claim 6, wherein the twosemiconductor pillars belonging to the set are formed as one body. 8.The device according to claim 6, wherein a length in the first directionof an end portion of the second electrode film on the semiconductorpillar side is shorter than a length in the first direction of an endportion of the second electrode film on the first electrode film side.9. The device according to claim 6, wherein an air gap is made in atleast one location between the semiconductor pillars, between the firstelectrode films adjacent to each other in the vertical direction, and/orbetween the second electrode films adjacent to each other in thevertical direction.
 10. The device according to claim 1, wherein thesecond electrode films are provided around the semiconductor pillar asviewed from above, and the first electrode films are provided around thesecond electrode films as viewed from above.
 11. The device according toclaim 1, wherein the second insulating film is not disposed between thefirst electrode film and the second electrode film for the uppermostlevel or for a plurality of levels including the uppermost level, andthe first electrode film is connected to the second electrode film forthe uppermost level or for the plurality of levels including theuppermost level.
 12. The device according to claim 1, wherein the secondinsulating film is divided along the vertical direction for each of thefirst electrode films.
 13. The device according to claim 1, furthercomprising: a cell source line provided between the substrate and thesemiconductor pillar to be connected to a lower end of the semiconductorpillar; a bit line provided on the semiconductor pillar to be connectedto an upper end of the semiconductor pillar; a third insulating filmprovided between the substrate and the cell source line; a source regionand a drain region formed to be separated from each other in a region ofthe substrate distal to a region directly under the semiconductorpillar; a fourth insulating film provided in a region directly above aregion of the substrate between the source region and the drain region;and a gate electrode provided on the fourth insulating film.
 14. Amethod for manufacturing a semiconductor memory device, comprising:forming a stacked body on a substrate by alternately stacking aninsulating film and a first film; making a first trench in the stackedbody to extend in a first direction; making a first recess by causing anexposed surface of the first film at an inner surface of the firsttrench to recede; forming a first insulating layer on the inner surfaceof the first trench; forming a first conductive film on the firstinsulating layer; removing a part of the first conductive film and apart of the first insulating layer located outside the first recess byetching and remaining another part of the first conductive film andanother part of the first insulating layer located inside the firstrecess; forming a first insulating film on the inner surface of thefirst trench; forming a semiconductor film on the first insulating film;making a second trench in the stacked body between the first trenches toextend in the first direction; making a second recess by removing thefirst film via the second trench; forming a second insulating layer onan inner surface of the second recess; forming a second conductive filminside the second recess; and dividing the semiconductor film and thefirst conductive film along the first direction, an equivalent oxidethickness of a second insulating film made of the first insulating layerand the second insulating layer being thinner than an equivalent oxidethickness of the first insulating film, a dielectric constant of thesecond insulating film being higher than a dielectric constant of thefirst insulating film.
 15. The method according to claim 14, furthercomprising filling an inter-layer insulating film into the first trenchafter the forming of the semiconductor film and prior to the making ofthe second trench, the making of the first trench including: forming afirst mask on the stacked body in a line-and-space configurationextending in the first direction; and performing anisotropic etchingusing the first mask, the dividing of the semiconductor film and thefirst conductive film along the first direction including: forming asecond mask on the first mask in a line-and-space configurationextending in a second direction intersecting the first direction; makinga through-hole by selectively removing the inter-layer insulating filmand the semiconductor film by performing anisotropic etching using thesecond mask and the first mask; and performing isotropic etching of thefirst conductive film via the through-hole.
 16. The method according toclaim 14, further comprising forming a second film on a back surface ofthe first recess after the making of the first recess and prior to theforming of the first insulating layer, the second film being made of amaterial different from a material of the first film, the making of thesecond recess including removing the first film using the second film asa stopper.
 17. A method for manufacturing a semiconductor memory device,comprising: forming a stacked body on a substrate by alternatelystacking an insulating film and a first conductive film; making a firsttrench in the stacked body to extend in a first direction; forming afirst insulating film on an inner surface of the first trench; forming asemiconductor film on the first insulating film; making a second trenchin the stacked body between the first trenches to extend in the firstdirection; making a recess by causing an exposed surface of the firstconductive film at an inner surface of the second trench to recede;forming a second insulating film on an inner surface of the recess, anequivalent oxide thickness of the second insulating film being thickerthan an equivalent oxide thickness of the first insulating film, adielectric constant of the second insulating film being lower than adielectric constant of the first insulating film; forming a secondconductive film inside the recess; and dividing the semiconductor filmand the first conductive film along the first direction.